The invention disclosed and claimed herein generally pertains to an apparatus and method for achieving direct frequency modulation of an output signal generated by a phase-locked loop (PLL) circuit. More particularly, the invention pertains to apparatus and method of the above type wherein the modulation signal comprises a digital sequence. Even more particularly, the invention pertains to apparatus and method of the above type wherein a counter is employed to selectively adjust the frequency divider of the PLL, in order to limit phase error signal levels.
Direct modulation of a voltage controlled oscillator (VCO) is very attractive since it simplifies the radio transmitter design, and thus may lower cost and power consumption. By changing the VCO input or control signal, a radio frequency (RF) carrier may be modulated, for example, to accomplish FM modulation. Typically, the VCO output frequency is proportional, although in a weakly non-linear fashion, to the input control signal. Thus, FM modulation may be accomplished by letting the control signal be proportional to the base-band signal. RF frequency has, however, to be accurately positioned at the correct channel frequency, and this is generally not possible with the VCO control signal accuracy achievable in mass production.
In order to control the VCO center frequency, the VCO may be used in a phase-locked loop (PLL) circuit. As is well known in the art, the phase-locked loop includes a tunable oscillator, typically a VCO, whose output signal is locked to a known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the two signals. The phase comparator output is fed back to the input of the VCO, through a loop filter H(s), as the VCO control signal. This locks the VCO output signal to the reference frequency, which thereby sets the accuracy of the VCO output frequency. By interposing a divide-by-N-block in the PLL circuit, the reference frequency may instead be compared with the VCO frequency divided by N, whereby the VCO output will be locked to N times the reference frequency. Moreover, by providing a divider control to vary N, it is possible to generate frequencies which are the Nth harmonic of the reference frequency where N is an integer.
If the VCO is modulated by adding a modulation signal Vmod to the VCO control signal, phase modulation of the PLL may be accomplished. With regard to frequency modulation, however, a PLL is in effect a control system that maintains a constant phase difference between two signals, so that any variations in the phase of one signal relative to the other are removed by the PLL. While this property of a PLL is useful in suppressing noise and cleaning up a signal, it also tends to suppress frequency modulation of a signal in a PLL circuit. Only if the modulation signal is fast compared to the looped filter, and the modulation signal has a zero mean, can the PLL act as an FM modulator. In the general case, however, this is not possible.
In view of these difficulties encountered in using a PLL for direct FM modulation, a technique has been developed wherein a compensation signal may be added to the phase detector error signal, such that the modulation signal component of the phase error is cancelled. This compensation signal may, however, grow quite large if the frequency deviation has a mean which is not close to zero. Furthermore, phase detector nonlinearities, such as the sinusoid response of a multiplying detector, have to be accounted for in an integrator constant K associated with operation of the VCO. These problems have generally prevented the widespread use of the compensation signal arrangement, which is known in the art as 2-point or 2-phase modulation of a PLL VCO.
In accordance with the invention, a modulation signal comprising a digital sequence is coupled to a bidirectional counter such as an up-down counter, to provide a compensation signal for the modulation-induced error. The compensation signal is then injected into the PLL from the counter output by means of a digital-to-analog (D/A) converter. The modulation component of the phase error signal will thereby be proportional to the counter output. When the counter output is a value corresponding to a modulation-induced error of 360 degrees, it sends a signal to the frequency divider control block of the PLL, whereupon the PLL divider is directed to divide the VCO output frequency by N+1 or Nxe2x88x921, rather than by N, depending on the sign of the error. This resets the error signal, and the counter is also reset. Thus, by exploiting the modulus 360 degree properties of the phase error, it is possible to limit the signal levels in the modulation compensation circuit used with the PLL.
By using analog modulation and digital compensation, the invention offers a less complex implementation resulting in reduced power consumption. The compensation employed in the 2-point modulation scheme of the invention is simple, and consists of an up-down counter and a D/A converter with a maximum output corresponding to a 360 degree phase error. Furthermore, simple direct FM modulation of a PLL can be accomplished at very high symbol rates, much higher than the reference frequency, with no limit to the FM burst length.
In one embodiment, the invention is directed to apparatus for selectively modulating the output signal of a VCO associated with a PLL circuit, which additionally comprises an adjustable frequency divider, a phase comparator, and a reference frequency source which determines the output signal frequency of the VCO. The apparatus comprises a counter coupled to receive a modulation signal comprising a train of digital symbols, the counter being driven by the modulation signal to produce an output corresponding thereto, the counter being further operated to generate a divider adjustment signal when the counter output reaches a specified value. The apparatus further comprises a first path for coupling a signal representing the digital modulation signal to the VCO input, a second path for injecting a compensation signal into the PLL for combination with the output of the phase comparator, and a divider control device for selectively adjusting the frequency divider in response to the adjustment signal.
In a preferred embodiment of the invention, the counter comprises an up-down counter and generates first and second adjustment signals when the counter produces first and second counter output values, respectively. The control device adjusts the divisor of the divider from N to N+1 and from N to Nxe2x88x921 in response to the first and second adjustment signals, respectively. The first and second counter output values respectively correspond to modulation-induced phase errors of +360 degrees and xe2x88x92360 degrees.
It should be emphasized that the term xe2x80x9ccomprises/comprisingxe2x80x9d when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.